The present invention is related in general to the field of semiconductor devices and processes and more specifically to structure and materials of high-performance plastic ball-grid array packages designed for integrated circuit assembly.
Ball Grid Array (BGA) packages have emerged as an excellent packaging solution for integrated circuit (IC) chips with high input/output (I/O) count. BGA packages use sturdy solder balls for surface mount connection to the xe2x80x9coutside worldxe2x80x9d (typically plastic circuit boards, PCB) rather sensitive package leads, as in Quad Flat Packs (QFP), Small Outline Packages (SOP), or Tape Carrier Packages (TCP). Some BGA advantages include ease of assembly, use of surface mount process, low failure rate in PCB attach, economic use of board area, and robustness under environmental stress. The latter used to be true only for ceramic BGA packages, but has been validated in the last few years even for plastic BGAs. From the standpoint of high quality and reliability in PCB attach, BGA packages lend themselves much more readily to a six-sigma failure rate fabrication strategy than conventional devices with leads to be soldered.
A BGA package generally includes an IC chip, a multi-layer substrate, and a heat spreader. The chip is generally mounted on the heat spreader using a thermally conductive adhesive, such as an epoxy. The heat spreader provides a low resistance thermal path to dissipate thermal energy, and is thus essential for improved thermal performance during device operation, necessary for consistently good electrical performance. Further, the heat spreader provides structural and mechanical support by acting as a stiffener, adding rigidity to the BGA package, and may thus be referred to as a heat spreader/stiffener.
One of the substrate layers includes a signal xe2x80x9cplanexe2x80x9d that provides various signal lines, which can be coupled, on one end, to a corresponding chip bond pad using a wire bond (or to a contact pad using flip-chip solder connection). On the other end, the signal lines are coupled with solder xe2x80x9cballsxe2x80x9d to other circuitry, generally through a PCB. These solder balls form the array referred to in a BGA. Additionally, a ground plane will generally be included on one of the substrate layers to serve as an active ground plane to improve overall device performance by lowering the inductance, providing controlled impedance, and reducing cross talk. These features become the more important the higher the BGA pin count is.
In contrast to the advantages of the BGA packages, prevailing solutions in BGA packages have lagged in performance characteristics such as power dissipation and the ability to maintain signal integrity in high speed operation necessary for devices such as high speed digital signal processors (DSP) and mixed signal products (MSP). Electrical performance requirements are driving the need to use multi-layer copper-laminated resin substrates (previously ceramic). As clock frequencies and current levels increase in semiconductor devices, the packaging designs are challenged to provide acceptable signal transmission and stable power and ground supplies. Providing stable power is usually achieved by using multiple planes in the package, properly coupled to one another and to the signal traces. In many devices, independent power sources are needed for core operation and for output buffer supply but with a common ground source.
As for higher speeds, flip chip assembly rather than wire bonding has been introduced. Compared to wire bonding within the same package outline, flip chip assembly offers greatly reduced IR drop to the silicon core circuits; significant reduction of power and ground inductances; moderate improvement of signal inductance; moderate difference in peak noise; and moderate reduction in pulse width degradation.
In order to satisfy all these electrical and thermal performance requirements, packages having up to eight metal layers have been introduced. The need, however, of high numbers of layers is contrary to the strong market emphasis on total semiconductor device package cost reduction. This emphasis is driving an ongoing search for simplifications in structure and materials, of course with the constraint that electrical, thermal and mechanical performances should be affected only minimally
In U.S. patent application Ser. No. 60/147,596, filed Aug. 6, 1999, to which this invention is related, the structure and fabrication method of a high-performance, high I/O plastic BGA has been discussed. There are only two metal layers, one of which is exclusively devoted to a ground plane. The package has thus a small thickness and a low cost. But the remaining metal layer has a crowded routing density, since all signal and power lines of the high I/O device have to share this one layer. Consequently, the Vcc inductances are too high for fast-speed processor devices. The high inductance is the source of unacceptable electrical noise and cross talk, severely limiting device speed.
The signal lines in today""s semiconductor package substrates suffer in their electrical performance (for instance, signal integrity and cross talk) because their characteristic impedance is not constant due to the fact that the lines have to be routed with non-uniform spacings to neighboring lines in the crowded line layout.
An urgent need has therefore arisen to break this vicious cycle and conceive a concept for a low-cost, yet high performance electrical connection on dielectric substrates, especially in BGA package structures. Preferably, this structure should be based on a fundamental design concept flexible enough to be applied for different semiconductor product families and a wide spectrum of design and assembly variations. It should not only meet high electrical and thermal performance requirements, but should also achieve improvements towards the goals of enhanced process yields and device reliability. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
According to the present invention, an electrical connection web is provided, operable at high frequency and configured on a dielectric substrate, comprising a plurality of generally parallel signal lines having graduated width and variable spacings, and said widths and spacings cooperatively selected such that the characteristic impedance of said signal lines is approximately the same for each line of said plurality and approximately constant over the length of each said signal line, whereby signal integrity for each said line is enhanced and cross talk between said lines is reduced.
According to electromagnetic theory, the impedance Z of an ac current of circular frequency xcfx89 is expressed by the relation
Z=(R2+X2)Exc2xd.
In this equation, the resistance R relates to the Ohmic resistance as modified by the high-frequency skin effect, and the reactance X relates to the inductance xcfx89L and the capacitance 1/xcfx89C as follows:
X=xcfx89Lxe2x88x921/xcfx89C.
With increasing frequency xcfx89, the contribution to the reactance X and the impedance Z by the inductance L is increasing, while the contribution by the capacitance C is decreasing.
The phase difference between current and voltage is usually denoted as "psgr". The following relations hold:
sin "psgr"=xe2x88x92X/Z;
cos "psgr"=R/Z;
xe2x80x83tg"psgr"=xe2x88x92X/R.
For two impedances Z1 (having resistance R1, reactance X1, and phase difference "psgr"1) and Z2 (having resistance R2, reactance X2, and phase difference "psgr"2) in series, the total impedance Ztotal is
Ztotal=[Z12+Z22+2Z1Z2 cos("psgr"1xe2x88x92"psgr"2)]Exc2xd.
For two impedances Z1 and Z2 in parallel, the total impedance Ztotal is
1/Ztotal=[1/Z12+1/Z22+2/(Z1Z2)cos("psgr"1xe2x88x92"psgr"2)]Exc2xd.
For designing signal lines in an IC package, it is useful to consider an individual line as being composed of several segments of uniform width and orientation. The impedance Zself of an individual line is then the sum of the segmental impedances in series.
Furthermore, it is useful to consider a plurality of lines as being composed of lines dependent on adjacent neighbors. The impedance Zmutual of the plurality is then the sum of the line impedances in parallel.
The characteristic impedance Ztotal of the signal lines in the package is then the sum of Zself and Zmutual:
Ztotal=Zself+Zmutual. (vector addition)
The package is commonly to be designed for a specific value of Ztotal. A signal travelling along a signal line would suffer distortions whenever the characteristic impedance Ztotal would not stay constant due to changes of either Zself and/or Zmutual.
The basic mathematics for calculating impedances for a layout of a plurality of conductors can be found in the paper by A. E. Ruehli, xe2x80x9cInductance Calculations in a Complex Integrated Circuit Environmentxe2x80x9d, IBM J. Res. Develop. Vol. 16, pp. 470-481 (1972). It is advantageous to obtain the solutions of the equations by a computer program.
In the calculation of the inductance of a conductor relative to a plane at ground potential, the relative geometry has to be considered. In this calculation, the inductance is expressed inversely proportional to the width, or area, of the conductor; consequently, the inductance can be reduced by increasing the area of the conductor.
It is an aspect of the present invention to keep Ztotal constant by compensating
any change of Zself through a counteracting change of Zmutual, and
any change of Zmutual through a counteracting change of Zself.
These counteracting changes are provided by cooperatively selecting widths and spacings of signal lines, thereby modifying the Ohmic and capacitive contributions to Zself and Zmutual with the goal of keeping the characteristic impedance approximately constant.
Another aspect of the invention is to provide a methodology to lower the inductance of the signal lines relative to the electrical ground potential by increasing the area of the line.
Another aspect of the invention is to utilize existing semiconductor fabrication processes and to reach the electrical device goals without the cost of equipment changes and new capital investment, by using the installed fabrication equipment.
Another aspect of the invention is to provide design and fabrication solutions such that they are flexible enough to be applied for different semiconductor high-performance device families and a wide spectrum of high speed, high power design and assembly variations.
These aspects have been achieved by the electrical design of the signal lines on dielectric substrates for high-speed semiconductor devices. In particular, the design according to the invention has been applied for the layout of high-speed signal lines on multi-layer substrates in high I/O ball grid array packages for high-performance integrated circuits.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.